The present invention relates to methods for separating a joined substrate type wafer for integrated circuit apparatuses with dielectrics. More particularly, the present invention relates to a methods of separating, with dielectrics, one of the semiconductor substrates of a wafer joined through an insulation film into a plurality of semiconductor regions which are insulated from each other.
Among conventional integrated circuit apparatuses, junction separation type wafers are usually used for separating the potential of regions housing a "built-in" semiconductor element or circuit. However, since the parasitic effects of known built-in transistors or diodes often cause trouble, and mindful that involved circuits often interfere with each other, dielectrics separation type wafers, especially the above described joined substrate type wafers, have been utilized within the context of integrated circuit apparatuses for high frequency use. Such devices are particularly suited to applications contingent upon high reliability over time.
Utilizing dielectrics separation type wafers to separate the inside of the integrated circuit apparatus into a plurality of mutually separated semiconductor regions shows that this is quite effective when done with dielectrics. Particular interest has been shown this approach among known devices, however, prominent difficulties remain.
The prominence of the extant difficulties among the devices of the prior art is demonstrated by reference to FIG. 3. FIG. 3 shows an example of the typical dielectrics separation type wafer according to the prior art. However, significant issues remain unadressed among the devices of the prior art. A brief perusal of conventional junction separation wafers clarifies the differences between the subject matters of the present invention and known apparatus.
As shown in FIG. 3, a joined substrate type wafer 10 is comprised of a semiconductor substrate 11, and an (n) type semiconductor substrate 13 jointed on the substrate 11 through an insulation film 12 of silicon oxide, lapped to a predetermined thickness and mirror polished to a thickness of 10 to several tens .mu.m.
The dielectrics separation of the wafer 10 is conducted as follows. Trenches 20 are dug by etching from the surface of the semiconductor substrate 13 down to the insulation film 12 to divide the substrate 13 to a plurality of semiconductor regions 14. The surface of each trench 20 is covered with dielectrics film 30 by thermal oxidation or similar methods which are known to those having a modicum of skill in the art. Subsequently, poly-crystalline silicon 40 is grown by a CVD method, or similar conventional process, so as to completely fill the trench 20 with the poly-crystalline silicon 40.
The deposition of the dielectrics film 30 and the growth of the poly-crystalline silicon 40 are conducted over the entire surface of the wafer 10. The dielectrics separation type wafer 60 of FIG. 3 is completed by removing the poly-crystalline silicon from the surface of the wafer 10. This step is undertaken to treat the entire surface of wafer 10, except the inside of each trench 20. This step involves a dry etching technique known as etching back, and further includes removing the dielectrics film 30 from the upper surface of the wafer 10. This step excludes the surface areas around each of the trenches 20 by chemical etching using a photoresistive film as a mask.
Referring now to FIG. 4, a sectional view showing the semiconductor regions 14 of the wafer 60 separated with dielectrics is shown. In this view, one can see that two MOS transistors are built in. Both transistors are separated by an element isolation film 61 which, is a local oxidizing film (LOCOS). On the left hand side of the local oxide film 61, a (p) type well 71 is diffused for an n-channel transistor. A gate oxide film 72 and gates 73 are disposed for the both transistors. A (p) type source and drain layers 74, 74 and an (n) type well connection layer 77 are disposed for a p-channel transistor shown on the right hand side, and an (n) type source and drain layers 76, 76 and a (p) type well connection layer 75 are disposed for an n-channel transistor shown on the left hand side.
Usually these transistors are covered with an inter-layer insulation film 81, and terminals S, D and G for a source, drain and gate are led out through windows opened in the film 81.
Longstanding problems remain to be solved by the subject matter of the present invention. Although the dielectrics separation type wafer according to the prior art shows an enhanced separation performance in terms of reducing the parasitic effects (or interference), production costs are prohibitive. Thus, each known prior art device has such an expensive cost that none have become accepted as cost efficient enough for practical use.
This is because of the excessively long time involved in separating the substrate of the wafer with dielectrics. This is especially true in attempts to grow the poly-crystalline silicon for filling trenches in removing the poly-crystalline silicon deposited on the unwanted areas.
Another drawback is that among conventional devices, precious areas of the wafer are often occupied by the separation trenches. Although the width of the separation trenches is generally from 5 to 15 .mu.m, the total occupied area is considerably wider, since the trenches are shaped with frames or a lattice surrounding the semiconductor regions.
In order to avoid this, instead of dividing the substrate 13 for each semiconductor element, the substrate 13 is usually divided for each circuit. Each circuit is comprised of a plurality of semiconductor elements as shown in FIG. 4. However, such known separation methods tends to cause the complication that the parasitic effects cannot be completely prevented.
In order to address these longstanding problems, the present invention provides a method of separating a semiconductor wafer with dielectrics. The present invention solves the problems described above which are inherent in known disclosures.
Further, prominent among the drawbacks of known dielectrics separation type wafers are the overall production costs. The present invention likewise reduces the overall cost of the dielectric separation processes, thus enhancing the economic utility of applicants' teachings.